PNNL, Micron Work on New Memory Architecture for Blended HPC/AI Workflows – HPCwire

Memory-bound computing performance has become the way of life in much of HPC. While processor speeds have improved, mostly through specialization and parallelism, the ability to move data to and from processors has not kept pace. This is especially true given the rise of blended AI/HPC workflows and their dependence on heterogeneous architectures. Now, a team of researchers from Pacific Northwest National Laboratory and memory technology vendor Micron began a project to help relieve this bottleneck.

Led by James Ang, PNNL’s chief scientist for computing, and Tom Brewer, Micron chief architect for near-data computing, the project intends to create a third level of memory hierarchy and leverage the CXL standard. There’s a brief account of the work in ASCRDiscovery.

[Update 3/12/20 project milestones added at end of article]

As Brewer explains. “The host would have some local memory, the GPU would have some local memory, but the main capacity memory is accessible to all compute resources across a switch, which would allow scaling of much larger systems.” This unified memory would let researchers using deep-learning algorithms to run a simulation while its results simultaneously feed back to the algorithm.”

Brewer said the Micron-PNNL collaboration will examine mixing old and new memory technologies to boost high-performance computing (HPC) workloads including efforts to “improve the memory devices themselves and efforts that look at how we can take traditional high-performance memory devices and run applications more efficiently.”

As described by the researchers, “In HPC systems that deploy AI, high-performance but low-capacity memory (typically gigabytes) is typically coupled to the GPUs, whereas a conventional system with low-performance but high-capacity memory (terabytes) is loosely coupled via the traditional HPC workhorses, central processing units (CPUs). [This project] will create proof-of-concept shared GPU and CPU systems and combine them with additional external storage devices in the hundreds of terabytes range. Future systems will need rapid access to petabytes of memory – a thousand times more capacity than on a single GPU or CPU.”

The researchers say a centralized memory system also benefits operations because an algorithm or scientific simulation can share data with, say, another program that’s tasked with analyzing those data. These converged application workflows are typical in DOE’s scientific discovery challenges. Sharing memory and moving it around involves other technical resources, says Andrés Márquez, a PNNL senior computer scientist. This centralized memory pool, on the other hand, would help mitigate the issue of over-provisioning the memory.

Ang told HPCwire that the CXL standard is gaining traction in HPC. A brief description of CXL is below the list of project milestones.

Link to ASCRDiscovery article,

Feature Image: A composite visual of a supercomputing testbed. Image courtesy of Jeff London/Pacific Northwest National Laboratory.


High Level Synthesis Milestones: 

  • Generation of specialized accelerators starting from high-level programming frameworks targeting Micron near memory design.
  • Automated generation of high-throughput custom accelerators for irregular kernels (sparse, graph analytics) for large (shared) memory pools
  • Extend automated generation of parallel accelerators with memory centric analysis to account for novel memory technologies (large memory pools, non-volatile memories, different memory hierarchies). Parallel accelerators include high-throughput architectures as well as dataflow based architectures.
  • Enable automated generation of complex designs including multiple intercommunicating near memory accelerators

Performance Analysis Milestones:

  • Memory (or location-based) “zooming” analysis to find “interesting” memory regions that have many accesses and that also have poor access patterns, poor spatio-temporal locality, or represent a similar bottleneck. Similarly, find memory regions that could be allocated within a scratchpad memory.
  • Memory system-level analysis and modeling by incorporating system-wide activity analysis and by applying automatic memory-centric and actor-centric diagnostics
  • Develop data object-based “zooming” analysis to attributing diagnostics to data objects. Capture traces of memory allocations and their call paths to associate memory regions with data objects
  • Identify potential control points within source code for pinpointing bottlenecks or for program adaptation by attributing memory analysis results to code regions.
    • Extend execution interval tree to include static/code features
    • Generate calling context tree representation
  • Develop analysis to target near-data computing for a GPU accelerator within fabric-attached memory. Collect memory address traces from NVidia GPU accelerators leveraging NVBit and perform location-based zooming.
  • Analysis and evaluation on AI/ML applications
    • DarkNet (C/C++ based):
    • AI/ML kernels on GPU accelerators near data
    • Translations of FPGA designs leveraging SODA’s x86 binaries

Scale Out Milestones:


  • Selection and initial design of programming model for a big memory accelerator
  • Prepare host’s distributed tasking and data movement infrastructure (leveraging the ARTS runtime system)


  • Explore high level interfaces on the compiler to extract detailed information about the workflow for multi granularity analysis
  • Identify and coordinate runtime/compiler interface with hardware and the rest of the software toolchain

Compute Express Link (CXL) is an open industry standard interconnect offering high-bandwidth, low- latency connectivity between host processor and devices such as accelerators, memory buffers, and smart I/O devices. It is designed to address the growing high-performance computational workloads by supporting heterogeneous processing and memory systems with applications in Artificial Intelligence, Machine Learning, Analytics, Cloud Infrastructure, Cloudification of the Network and Edge, communication systems, and High Performance Computing. It does this by enabling coherency and memory semantics on top of the PCI Express (PCIe) 5.0 based I/O semantics for optimized performance in evolving usage models. This is increasingly important as processing data in these emerging applications requires a diverse mix of scalar, vector, matrix and spatial architectures deployed in CPU, GPU, FPGA, smart NICs, and other accelerators.

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